PNP lateral bipolar electronic device

ABSTRACT

A lateral PNP bipolar electronic device integrated monolithically on a semiconductor substrate together with other NPN bipolar devices capable of being operated at high frequencies. The PNP device is incorporated to an electrically insulated multilayer structure which comprises a semiconductor substrate, doped for conductivity of the P-type, a first buried layer, doped for conductivity of the N-type to provide a base region, and a second layer, overlying the first and having conductivity of the N-type, to provide an active area distinguishable by a P-doped emitter region within the active area being located peripherally and oppositely from a P-doped collector region. The lateral PNP device can be operated at high frequencies with suitable collector current values and good amplification, to provide a superior figure of merit compared to that typical of conventional lateral PNP devices.

TECHNICAL FIELD

1. This invention relates to a PNP bipolar electronic device.

2. In particular, the invention relates to a lateral PNP bipolarelectronic device which is integrated monolithically on a semiconductorsubstrate together with other bipolar devices of the NPN type.

BACKGROUND OF THE INVENTION

3. As is well known, NPN transistors are preferred for implementingintegrated circuitry of the bipolar type on semiconductor substrates, onaccount of their DC and AC amplifications being definitely better thanthose of PNP transistors.

4. Another disadvantage of PNP bipolar transistors is their closelimitations in high frequency applications.

5. Despite all this, the inclusion of both NPN and PNP transistors on acommon semiconductor substrate is still a necessity where suitable biascircuits, current mirror circuits and/or load devices for gain stagesare to be provided.

6. The formation of PNP transistors on a semiconductor substrate iseffected concurrently with that of NPN transistors, without anyadditional implanting or masking steps.

7. It is for this reason that it has become common practice to form PNPbipolar transistors of the so-called lateral type such that they can becompatible with the process flows adopted to fabricate NPN bipolardevices.

8. In this respect, FIG. 1 shows an enlarged cross-sectional view, takenon a vertical plane, of a sidewall PNP device 6 formed on a P-dopedsemiconductor substrate 1.

9. The following are successively deposited onto this substrate 1: afirst buried layer 2 doped N+ to form the base region of the transistor,and a second layer 3, doped N, which constitutes the active area of thePNP device to be.

10. Thereafter, a selective diffusion of P-type dopants is realized inthe active area 3 to define a central emitter region 4 surrounded by twoopposite collector regions 5.

11. This solution has been widely used heretofore, to the point that atext, “Design and Realization of Bipolar Transistors”, Peter Ashburn,page 157, gives it as the principal configuration for a lateral PNPdevice that can ensure of a good current gain.

12. It should be noted that such lateral PNP transistors have anintrinsic current loss of about 3% compared to collector current; thesecurrents can also be explained theoretically by having reference to thediagram in FIG. 2 of an equivalent electric circuit of a lateral PNPtransistor.

13. It can be seen in this figure that the lateral PNP device,designated Q₁ in the equivalent circuit, is connected to a pair ofparasitic PNP transistors Q₂ and Q₃ having their respective emitterregions connected to the emitter and collector regions of the transistorQ₁.

14. In addition, these parasitic devices Q₂ and Q₃ have their collectorregions connected to the semiconductor substrate, and their base regionsin common with the base of Q₁.

15. This equivalent electric diagram shows that the parasitic currentsare mainly attributable to the second parasitic device Q₂ drainingtoward the substrate some of the current being injected by the emitterof Q ₁, thereby lowering the efficiency of lateral emission.

16. Similar considerations apply to the third parasitic device Q₃, whichcontributes instead to lowering the collection efficiency of thecollector of Q₁ when the latter is biased to its saturation range.

17. To overcome drawbacks of this kind, tied to the parasitic currents,a conventional solution has been that of optimizing the collectionefficiency of the carriers in the collector region, so as to maximizethe gain of lateral transistors.

18. For this reason, lateral PNP transistors have been implementedconventionally with their emitter region occupying, in the active area,a central location surrounded by two collector regions.

19. While being in many ways advantageous, this prior solution has aserious drawback in that it leads to increased values of certaincharacteristic parameters of the lateral PNP device, such as thebase-collector and emitter-base capacitances, C_(bc) and C_(eb), whichrestrict performance at high frequencies.

20. This drawback is also connected with the considerable spread of thebase region in the buried layer brought about by the need to control thelateral PNP device performance in the emitter and collector regions.

21. Especially the width W_(b) of this base region adversely affects thecarrying parameter B*, which is tied to W_(b) by the following formula:$\begin{matrix}{B^{*} \approx {1 - \frac{W_{b}^{2}}{2D\quad \tau}}} & (1.1)\end{matrix}$

22. where D is the diffusion value, and τ is the re-combination time ofthe carriers.

23. It should be noted that the B* factor is inversely proportional tothe passage time through the base region, so that as it increases, thefrequency performance of the lateral PNP device deteriorates.

24. Unfortunately, this type of lateral PNP device revealed seriouslimitations when attempts were made to improve its high frequencyperformance.

25. These limitations come from the practical impossibility of bringingthe collector regions closer to the central emitter region.

26. This is both attributable to the photolithographic masks used fortransferring the patterns of the active region, and side diffusioneffects during the formation of the emitter and collector regions, aswell as to breakdown effects which may occur in the region between thebase and the collector.

27. As a result, the width W_(b) of the base region of the lateral PNPtransistors always exhibits values between 2 μm and 4 μm.

28. Another problem to be taken into account is that the central emitterregion includes neighboring regions with a predetermined width E_(C),due to the “bird's beak” phenomenon.

29. These regions cause the minimum width W_(AA) of the active arearequired for containing the central emitter region (see example in FIG.7) to be increased, which further harms the device performance.

30. Thus, it has become good designing practice to never put an activearea minimum width W_(AA) at anything below the limit given by thefollowing formula (1.2), taking account of the actual width of theemitter contact region CNTWidth and of the added width E_(C) due to the“bird's beak”.

W>CNTWidth+2*Ec  (1.2)

31. To this regard, the electron microphotograph of FIG. 3 comes usefulwhich shows an enlarged cross-section through a typical lateral PNPdevice taken near the central emitter region.

32. In the present instance, it can be seen that the “bird's beak”inside the active area extends for about 0.6 μm and, therefore, requiresa minimum width W_(AA) greater than about 2.6 μm.

SUMMARY OF THE INVENTION

33. An embodiment of this invention provides a new topographyconferring, on a lateral PNP device, such structural and functionalfeatures as to make it suitable for high frequency applications as well,thereby overcoming the aforesaid limitations and drawbacks.

34. An embodiment of this invention provides a lateral PNP devicetopography which is compatible with NPN process flows and allows anemitter region to be located peripherally of the active area of thedevice rather than centrally.

35. In one embodiment of the invention, an electronic device isincorporated into an electrically insulated multilayer structure. Theelectronic device comprises a semiconductor substrate doped withimpurities of the P-type, a first buried layer doped with impurities ofthe N-type to provide a base region, and a second layer, overlying thefirst and having conductivity of the N-type, to provide an active areawherein a P-type emitter region is located peripherally in the activearea at an opposite location from a P-type collector region.

36. It thus becomes possible to improve those characterizing parametersof PNP devices that previously imposed restrictions on their use at highfrequencies.

37. Advantageously, the design of the lateral PNP device of thisinvention provides a better figure of merit than conventional lateralPNP transistors.

38. The features and advantages of the inventive device will be apparentfrom the following description of an embodiment thereof, given by way ofnon-limitative example with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

39.FIG. 1 is an enlarged-scale sectional view taken on a vertical planeof a lateral PNP device integrated on a semiconductor substrate,according to the prior art.

40.FIG. 2 shows a schematic equivalent electric circuit of a lateral PNPdevice integrated on a semiconductor substrate, according to the priorart.

41.FIG. 3 is an electron microphotograph of a central emitter region ofa prior art lateral PNP device.

42.FIG. 4 is an enlarged-scale sectional view taken on a vertical planeof a lateral PNP device integrated on a semiconductor substrate,according to the invention.

43.FIG. 5 is an enlarged cross-sectional view of the emitter region ofthe PNP device according to the invention.

44.FIG. 6 is a plan view of a semiconductor substrate incorporating thePNP device of this invention which highlights the emitter regionthereof.

45.FIG. 7 is a plan view of a semiconductor substrate incorporating alateral PNP device with a central emitter region, according to the priorart.

DETAILED DESCRIPTION OF THE INVENTION

46. Referring to FIG. 4, a preferred embodiment of a lateral PNP device15, monolithically integrated on a semiconductor substrate together withother NPN devices (not shown because conventional), which can also beoperated at high frequencies, will be described.

47. A multilayer structure 17, electrically isolated from any otherintegrated device by the selective growing of isolation oxide regions11, has been formed on a P-doped semiconductor substrate 10.

48. This multilayer structure is produced by the successive deposition,onto the substrate 10, of a first buried layer 12 doped for conductivityof the N-type to form a base region, and of a second layer 13 withconductivity of the N-type which represents an active area of thelateral PNP device 15.

49. The fabrication process includes the definition of an emitter region14 and a collector region 16. To define the emitter and collectorregions 14, 16, a first step of selectively diffusing P-type dopants iscarried out onto the surface of the active area.

50. At the end of this operation, the emitter region 14 will locateperipherally of the active area 13, opposite from the collector region16.

51. To complete the lateral PNP device 15, a second step of diffusing Ndopants is carried out so as to have a base region 20 of the firstburied layer 12 extend to the top of the multilayer structure.

52. In order for the lateral PNP device 15 to accommodate any futureelectric connections to other integrated devices on the substrate 10, acontact forming step is necessary.

53. This step is carried out conventionally to provide polysiliconelectric contacts at the locations of the emitter 14, collector 16 andbase 20 regions. The contacts are formed in predetermined areas of themultilayer structure top, taking care to provide an emitter contact 21externally of the multilayer structure of the PNP device 15 as definedby the isolation oxide regions 11.

54. The layout described so far has the advantage of reducing thecapacitive parameters, C_(be) and C_(bc), associated with the lateralPNP device 15 which were the main cause of limitation to performance athigh frequencies.

55. The solution proposed herein may seem a tradeoff of the collectionefficiency brought about by a single collector region 16 (hence, aninferior collector current) in favor of improved performance at highfrequencies.

56. This potential drawback is illustrated in greater detail by FIGS. 5and 6, which show a region of the emitter 14 in cross-section and planviews, respectively.

57. The emitter region 14 is preferably rectangular in plan form, with awidth We smaller than its length Le. This region 14 locates oppositefrom the central collector region 16 (omitted from FIGS. 5 and 6).

58. In this way, the “lateral transistor effect” has been improved, andthe collector current increased accordingly, since both these effectsbenefit from an elongate geometry of the emitter region 14.

59. It should also be noted that this geometry of the emitter region 14has added advantages to further reduce the value of the capacitiveparameter C_(eb) and to reduce current leakage toward the substrate 10.

60. The results of tests carried out by the Applicants with the lateralPNP device 15 have confirmed advantages of this solution.

61. In particular, it has been possible to ascertain that an optimumcondition is achieved with a high ratio (P/A) of the active periphery Pto the surface area A of the emitter region 14.

62. The term ‘active periphery P’ is used herein to indicate thatportion of the emitter region 14 perimeter which is facing the collectorregion 16 directly.

63. In the lateral PNP device 15 of this invention, this P/A ratio canreach very high values, previously unattainable by a standard PNP devicehaving a central emitter region.

64. More particularly, the P/A ratio is equal to a constant, l/W_(e),obtained from respective values of P and A equal to L_(e) andW_(e)*L_(e).

65. Simple calculations, assuming W_(e) to be 0.4 μm in one case, and0.15 μm in another, yield values of P/A of 2.5 μm and 6.7 μm,respectively.

66. These results are made possible by the proposed configurationproviding a peripheral location for the emitter region 14 in the activearea, concurrently with moving the emitter contact 21 outside of themultilayer structure 17 defined by the isolation oxide regions 11.

67. It should be noted, in particular, that by having the emitter region14 moved to the periphery of the active area 13 (see FIGS. 6 and 7), thequantity W_(AA), mentioned under the Background of the Invention headingabove, which represents the minimum width for the active area, can bereduced.

68. This allows the size of the lateral PNP device described hereinaboveto be also reduced, thereby further improving its frequency performance.

69. In conclusion, this lateral PNP device can be operated at highfrequencies, with suitable collector current values and goodamplification, to provide a superior figure of merit compared to thattypical of conventional lateral PNP devices.

70. From the foregoing it will be appreciated that, although specificembodiments of the invention have been described herein for purposes ofillustration, various modifications may be made without deviating fromthe spirit and scope of the invention. Accordingly, the invention is notlimited except as by the appended claims.

What is claimed is:
 1. A lateral PNP bipolar electronic deviceintegrated monolithically on a semiconductor substrate together withother bipolar devices of the NPN type, said device being incorporated toan electrically insulated multilayer structure which comprises: thesemiconductor substrate, doped with impurities of the P-type; a firstburied layer, doped with impurities of the N-type to provide a baseregion; and a second layer, overlying the first buried layer and havingconductivity of the N-type, to provide an active area, wherein withinsaid active area, a P-doped emitter region is located peripherally ofthe active area at an opposite location from a P-doped collector region.2. The lateral PNP bipolar electronic device according to claim 1 ,further comprising an electric contact of the emitter region extendinglaterally of said active area.
 3. The lateral PNP bipolar electronicdevice according to claim 1 wherein the emitter region has acorresponding electric contact extending externally of the electricallyinsulated multilayer structure.
 4. The lateral PNP bipolar electronicdevice according to claim 1 wherein said emitter region has anessentially rectangular plan form.
 5. The lateral PNP bipolar electronicdevice according to claim 4 wherein said emitter region is elongatealong one direction to span a full length of the oppositely locatedcollector region along said one direction.
 6. A lateral PNP bipolardevice integrated monolithically on a semiconductor substrate,comprising: an N-type active area formed above the semiconductorsubstrate, the active area including a top side extending from a firstlateral end to a second lateral end; a P-type collector region formed atthe top side of the active area; and a P-type emitter region formed atthe top side of the active area and immediately adjacent to the firstlateral end of the active area.
 7. The lateral PNP bipolar device ofclaim 6 wherein said semiconductor substrate is doped with impurities ofthe P-type and the lateral PNP bipolar device further includes: adielectric region for insulating said lateral PNP bipolar device fromother devices on the semiconductor substrate, the dielectric regionbeing positioned adjacent to the active region; a buried first layerformed on the semiconductor substrate and doped with N-type impuritiesto provide a base area; and a second layer formed on the first buriedlayer and doped with N-type impurities to provide the active area. 8.The lateral PNP bipolar device of claim 7 , further comprising anemitter contact electrically coupled to the emitter region andpositioned opposite to the active region with respect to the dielectricregion.
 9. The lateral PNP bipolar device of claim 6 , furthercomprising an emitter contact electrically coupled to the emitter regionand positioned laterally of the active area.
 10. The lateral PNP bipolardevice of claim 6 wherein said emitter region is substantially arectangular form.
 11. The lateral PNP bipolar device of claim 10 whereinsaid emitter region extends along one direction to a full length of theoppositely located collector region in the one direction.
 12. Thelateral PNP bipolar device of claim 10 wherein the emitter regionincludes first and second sides, the first side facing a side of thecollector region and being longer than the second side.
 13. A method formanufacturing a lateral PNP bipolar device integrated monolithically ona semiconductor substrate, comprising: preparing a semiconductorsubstrate doped with P-type impurities; forming dielectric regions toinsulate said bipolar device from other devices; forming a buried firstlayer doped with N-type impurities for defining a base region; formingan N-type second layer within the first buried layer to define an activearea; forming a collector region within the active area; and forming anemitter region peripherally located within the active area and adjacentto one of the dielectric regions, said emitter region extendinglaterally in the active area in a direction parallel to the collectorregion.
 14. The method of claim 13 , further comprising: forming a basecontact region in contact with the buried first layer; forming acollector contact electrically coupled to the collector region; andforming an emitter contact electrically coupled to the emitter region.15. The method of claim 14 wherein the act of forming an emitter contactincludes forming the emitter contact opposite to the active region withrespect to the one of the dielectric regions.